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This doctoral thesis explores the design and implementation of phase-locked loops (PLLs) and millimeter-wave PLL components tailored for 60-GHz wireless networks using CMOS technology. The work addresses the challenges of achieving multi-gigabit per second wireless transmission in the 60 GHz license-free frequency band. It presents a systematic top-down approach, starting with system analysis, followed by the design and implementation of critical synthesizer components, and culminating in the integration of these components to form a complete synthesizer. The thesis provides insights into layout parasitic, measurement techniques at millimeter-wave frequencies, and the design of various PLL components, including prescalers, voltage-controlled oscillators, and feedback loops. The research contributes to the advancement of CMOS-based solutions for high-frequency wireless communication applications.

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245: $a: 60-GHz CMOS Phase-Locked Loops
245: $b:
082: $a:
100: $a: Hammad M. Cheema
650: $a: Computer Science
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440: $v:
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250: $c: 2010
020: $a: 978-90-386-2143-2
300: $a: 206